This invention pertains to color video graphics, and more particularly to a high speed RAMDAC circuit capable of providing both a true color mode and a high speed pseudo color mode.
A typical raster display system 10 known to those skilled in the art of color graphics is shown in FIG. 1. Display system 10 includes a general-purpose CPU 12 and a special-purpose display processor 16 coupled to the system bus 14. The special-purpose display processor 16 performs graphics functions such as scan conversion and raster operations. Display system 10 includes three memory locations: the system memory 22, which contains the application program, graphics package, and operating system; the display processor memory 18, which contains programs that perform the scan and raster operations; and the frame buffer 20, which contains the displayable image created by the scan conversion and raster operations. The video controller 24 converts data from the frame buffer 20 into R, G, and B analog signals and H and V digital synch pulses. The analog RGB signals control the color and intensity of the CRT beam and resultant displayed pixels on the CRT color monitor 26. The R, G, and B signals represent the intensity of the separate red, green, and blue electron beams guns in the CRT color monitor. The combination of the intensities produced by each gun result in the color of a particular pixel at a particular location. While the RGB color coordinate system is widely used to organize video color data, other color coordinate systems are used as well. The alternative HIS color coordinate system expresses colors as a function of hue, intensity, and saturation. The horizontal and vertical (H and V in FIG. 1) signals are digital synch pulses for triggering the horizontal and vertical analog control circuitry, typically placed within the monitor 26. The horizontal and vertical control circuits sweep the beam across and down to cover the entire screen of monitor 26 at a typical "frame rate" of sixty times a second.
The video controller 24 is shown in further detail in FIG. 2. The video controller essentially consists of a RAMDAC 30 for generating the R, G, and B analog signals, a video timing generator 28 for generating the H and V digital synch pulses at terminals 27 and 29 as well as a video clock 42, and a display refresh address generator 8. The RAMDAC 30 and the video timing generator 28 receive data from the frame buffer through the video bus 25. The display refresh address generator 8 provides a sequence of addresses to the frame buffer 20 on address bus 23 in order that the data is presented to the RAMDAC 30 in the proper display sequence.
The RAMDAC 30 includes a random access memory ("RAM") 32, such as a 256 by 24 RAM (also known as a "color palette") for receiving eight bits of information and generating three eight bit outputs, which are coupled to three digital-to-analog converters ("DACs") 34, 36, and 38. Each DAC converts the digital information from RAM 32 into appropriate analog signals for driving the video inputs of color monitor 26 at terminals 35, 37, and 39, respectively labeled R, G, and B. The outputs of the RAMDAC 30 are typically current outputs, which are converted into analog voltages when coupled to an appropriate load resistor. The RAMDAC 30 can include input latch circuits, input multiplexers, and other circuits for generating additional functions such as text overlay and cursor. An example of a typical RAMDAC circuit is the Bt468 integrated circuit manufactured by Brooktree Corporation of San Diego, Calif.
The RAMDAC 30 is shown in still further detail in FIG.3. In addition to RAM 32 and DACs 34, 36, and 38, RAMDAC 30 typically includes an input shift register 6. At higher operating speeds in the hundreds of megahertz, it is difficult for ordinary TTL type circuits to directly drive the eight bit input of RAM 32. Therefore input shift register 6 converts a sixty-four bit parallel input bus into an eight bit bus that can be used by RAM 32. In this manner, the effective maximum frequency rate of the data presented to RAMDAC 30 is divided by a factor of eight. This lower input frequency is generally within the range of operation of most TTL driver circuits.
Raster scan display systems are typically configured to provide either a "true color" mode or a "pseudo color" mode. The pseudo color mode is best described with reference to FIG. 2. Note that RAM 32 has one data input and three data outputs. The input bus to RAM 32 is typically eight bits wide, which carries an address that specifies the color of the pixel being displayed. The RAM 32 serves as a "color lookup table" or "color palette" wherein the 2.sup.8 (256) possible addresses are transformed into color choices out of a possible 2.sup.24 (16,777,216) total colors. Therefore, each address location in RAM 32 contains a twenty-four bit data word, which represent the red, green, and blue color components. The pseudo color mode is used in applications where fine gradations in color are necessary, but large numbers of colors are not needed. An example of an image not requiring large numbers of colors is an engineering diagram wherein the images are largely comprised of lines or boxes. The RAM 32 can be continually reprogrammed (only once for each video frame) to provide new color palettes as needed for new colors appropriate to the image being displayed.
In contradistinction to the pseudo color mode, the true color mode typically provides several bits (at least five, typically eight) for each of the red, green, and blue color components to provide fine gradations in all color components. All colors (over sixteen million for twenty-four bit true color) are always available and therefore any pixel in the frame may be assigned any color. True color mode is often required for realistic images having extreme variations in color and intensity.
One RAMDAC circuit for creating true color mode is shown in FIG. 4. Color graphics circuit 40 replaces a single RAMDAC and includes first, second, and third RAMDACs 30A, 30B, and 30C. Each RAMDAC receives eight bits from the video bus 25 for the corresponding red, green, and blue color components. Note that a wider, 192 bit (effectively twenty-four bit at the output of the shift register) parallel bus is required for the true color mode. Each RAMDAC 30A-30C is programmed to transfer the address data directly through the internal RAM to the corresponding DAC. Alternatively, the internal RAM can be programmed to provide "gamma correction", which corrects the nonlinearities in the color monitor 26 with respect to the applied analog video signal, or the internal RAM can be programmed to enhance the contrast of the displayed graphics image, which is sometimes used in medical imaging applications. In any case, each output 35, 37, and 39 carries an analog voltage representing eight bits of color information for driving the respective video input of the color monitor 26. Another way of creating true color mode is similar to the circuit shown in FIG. 3, but each RAMDAC is replaced by a VIDEODAC, which is essentially an input register directly coupled to three high-speed DACs. The VIDEODACs do not provide gamma correction or image enhancement.
One trend in color video graphics is to attempt to increase the resolution of the image displayed on the color monitor 26 for the purpose of increasing the clarity and realism of the displayed image. However, to increase resolution, the number of pixels on the screen of the monitor 26 is increased. Furthermore, the frame rate can be increased from 60 Hz to 70 Hz or even higher frequencies to reduce flicker. Either approach of improving the quality of the displayed image thereby increases the frequency of the video signals provided by the RAMDAC 30. The increased operating speed necessary for increased resolution is applicable to both the true color and pseudo color modes.
The highest speed commercially available RAMDAC circuits, compared to the lower speed counterparts, tend to be more costly, consume more power, and are lacking certain desirable features such as hardware cursors and a self-test mode. These functions, if implemented in external hardware, further increase the cost and complexity of graphics systems based on these high-speed RAMDACs.
Another trend in color video graphics is to combine both the true color and pseudo color modes in one video graphics system. Such a system can easily convert from displaying high resolution line drawing of the pseudo color mode with a limited number of available simultaneous colors to displaying realistic images with the full choice of colors available in the true color mode.
User selectable true color and pseudo color modes are provided by advanced integrated circuits that are typically characterized by one or more of the following undesirable attributes: extremely high pin count, low output operating speed, or high video input data bus frequency that is higher than the operating speed of conventional TTL driver circuitry.
Another approach for providing true color and pseudo color modes uses a novel data compression technique for compressing the normal twenty-four bits of true color data into eight bits for use with a normal RAMDAC. However, since the calculations for the data compression are done in the display processor, operating speed is lowered. In addition, certain pathological cases exists that cannot be compressed with existing techniques.
Furthermore, the problem of combining the two color modes only increases as resolution increases. In addition to the problems mentioned above, the problem of providing data to the RAMDAC becomes even more significant. As the number of pixels increases, the frequency of the input data further increases above that which is possible with commercially available TTL based logic blocks. Therefore, either special circuitry must be used in conjunction with the video bus, increasing cost and complexity, or the input bus be configured to be massively parallel. The parallel bus also increases circuit complexity, since additional input registers, latches, and memory are required to convert the massively parallel input data to serial eight bit data suitable for use with the RAMDAC. In addition, the number of pins required by such a part rapidly increases, which also increases cost and complexity.
Therefore, what is desired is a high speed graphics circuit that can provide both high speed pseudo and true color modes using commercially available parts without special circuitry or requiring a significant increase in cost, power, or a loss of functionality.